In the field of horizontal FETs of high voltage endurance and low on-resistance, there have been constant attempts to improve the results of the inevitable tradeoffs between voltage endurance and on-resistance per unit. In the following description, (n) or (p) preceding layer or region names indicates that electrons or holes, respectively, are majority carriers in those layers or regions.
FIG. 5 shows a cross-section of a p-channel type DMOSFET which is an example of a conventional horizontal FET. The p-type substrate 401 is a silicon wafer with a resistivity of 15 .OMEGA..multidot.cm. N-type impurities, e.g., phosphorus, are injected into the surface layer of the p-type substrate 401 to form n well region 402. The n well region 402 has a surface concentration of 3.times.10.sup.16 cm.sup.-3 and a diffusion depth x.sub.j of about 4 .mu.m. In addition, an n base region 405, a p offset region 406, a p source region 403 and a p drain region 404 are formed on the surface of the n well region 402 by selective ion injection, using a mask. The n base region 405 has a surface concentration of 1.times.10.sup.17 cm.sup.-3 and a diffusion depth x.sub.j of about 1 .mu.m. The p offset region 406 has a surface concentration of 5.times.10.sup.16 cm.sup.-3 and a diffusion depth x.sub.j of 0.6 .mu.m.
A gate electrode 408 is formed on a gate oxide film 407, and its drain side is formed on a thick oxide film LOCOS 409. The p offset region 406 (the drain drift region) protrudes about 1 .mu.m from the LOCOS 409 towards the source side. The distance Lga between the gate electrode 408 and the LOCOS 409 is about 2 .mu.m, and the length LLOCOS of the LOCOS 409 is about 1 .mu.m.
For voltage resistance of several tens of volts, attempts have been made to improve the tradeoffs by further shrinking the elements (reducing the gate length Lga or a drain drift length Ld.apprxeq.LLOCOS) or by optimizing the concentration of impurities in the p offset region 406 and the n base region 405. In the p-channel type MOSFET, however, since the gate length Lga is reduced and the concentration of the p offset region 406 is increased, punchthrough voltage endurance is significantly degraded, preventing any further reduction in the size of the elements. Punchthrough voltage resistance is improved by increasing the base concentration (the concentration of impurities in the base region), but the increase in base concentration may raise threshold voltage, and thus channel resistance, when a gate drive voltage is constant.
The object of this invention is to provide a horizontal FET with high voltage endurance and low on-resistance in which the tradeoff between voltage endurance and on-resistance is improved by improving punchthrough voltage endurance or by further reducing the size of elements to reduce on-resistance.